Struct cudaDeviceAttr

#[repr(transparent)]
pub struct cudaDeviceAttr(pub c_uint);

CUDA device attributes

Tuple Fields

0: c_uint

Implementations

impl cudaDeviceAttr

pub const cudaDevAttrMaxThreadsPerBlock: cudaDeviceAttr

< Maximum number of threads per block

impl cudaDeviceAttr

pub const cudaDevAttrMaxBlockDimX: cudaDeviceAttr

< Maximum block dimension X

impl cudaDeviceAttr

pub const cudaDevAttrMaxBlockDimY: cudaDeviceAttr

< Maximum block dimension Y

impl cudaDeviceAttr

pub const cudaDevAttrMaxBlockDimZ: cudaDeviceAttr

< Maximum block dimension Z

impl cudaDeviceAttr

pub const cudaDevAttrMaxGridDimX: cudaDeviceAttr

< Maximum grid dimension X

impl cudaDeviceAttr

pub const cudaDevAttrMaxGridDimY: cudaDeviceAttr

< Maximum grid dimension Y

impl cudaDeviceAttr

pub const cudaDevAttrMaxGridDimZ: cudaDeviceAttr

< Maximum grid dimension Z

impl cudaDeviceAttr

pub const cudaDevAttrMaxSharedMemoryPerBlock: cudaDeviceAttr

< Maximum shared memory available per block in bytes

impl cudaDeviceAttr

pub const cudaDevAttrTotalConstantMemory: cudaDeviceAttr

< Memory available on device for constant variables in a CUDA C kernel in bytes

impl cudaDeviceAttr

pub const cudaDevAttrWarpSize: cudaDeviceAttr

< Warp size in threads

impl cudaDeviceAttr

pub const cudaDevAttrMaxPitch: cudaDeviceAttr

< Maximum pitch in bytes allowed by memory copies

impl cudaDeviceAttr

pub const cudaDevAttrMaxRegistersPerBlock: cudaDeviceAttr

< Maximum number of 32-bit registers available per block

impl cudaDeviceAttr

pub const cudaDevAttrClockRate: cudaDeviceAttr

< Peak clock frequency in kilohertz

impl cudaDeviceAttr

pub const cudaDevAttrTextureAlignment: cudaDeviceAttr

< Alignment requirement for textures

impl cudaDeviceAttr

pub const cudaDevAttrGpuOverlap: cudaDeviceAttr

< Device can possibly copy memory and execute a kernel concurrently

impl cudaDeviceAttr

pub const cudaDevAttrMultiProcessorCount: cudaDeviceAttr

< Number of multiprocessors on device

impl cudaDeviceAttr

pub const cudaDevAttrKernelExecTimeout: cudaDeviceAttr

< Specifies whether there is a run time limit on kernels

impl cudaDeviceAttr

pub const cudaDevAttrIntegrated: cudaDeviceAttr

< Device is integrated with host memory

impl cudaDeviceAttr

pub const cudaDevAttrCanMapHostMemory: cudaDeviceAttr

< Device can map host memory into CUDA address space

impl cudaDeviceAttr

pub const cudaDevAttrComputeMode: cudaDeviceAttr

< Compute mode (See ::cudaComputeMode for details)

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture1DWidth: cudaDeviceAttr

< Maximum 1D texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DWidth: cudaDeviceAttr

< Maximum 2D texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DHeight: cudaDeviceAttr

< Maximum 2D texture height

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture3DWidth: cudaDeviceAttr

< Maximum 3D texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture3DHeight: cudaDeviceAttr

< Maximum 3D texture height

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture3DDepth: cudaDeviceAttr

< Maximum 3D texture depth

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DLayeredWidth: cudaDeviceAttr

< Maximum 2D layered texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DLayeredHeight: cudaDeviceAttr

< Maximum 2D layered texture height

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DLayeredLayers: cudaDeviceAttr

< Maximum layers in a 2D layered texture

impl cudaDeviceAttr

pub const cudaDevAttrSurfaceAlignment: cudaDeviceAttr

< Alignment requirement for surfaces

impl cudaDeviceAttr

pub const cudaDevAttrConcurrentKernels: cudaDeviceAttr

< Device can possibly execute multiple kernels concurrently

impl cudaDeviceAttr

pub const cudaDevAttrEccEnabled: cudaDeviceAttr

< Device has ECC support enabled

impl cudaDeviceAttr

pub const cudaDevAttrPciBusId: cudaDeviceAttr

< PCI bus ID of the device

impl cudaDeviceAttr

pub const cudaDevAttrPciDeviceId: cudaDeviceAttr

< PCI device ID of the device

impl cudaDeviceAttr

pub const cudaDevAttrTccDriver: cudaDeviceAttr

< Device is using TCC driver model

impl cudaDeviceAttr

pub const cudaDevAttrMemoryClockRate: cudaDeviceAttr

< Peak memory clock frequency in kilohertz

impl cudaDeviceAttr

pub const cudaDevAttrGlobalMemoryBusWidth: cudaDeviceAttr

< Global memory bus width in bits

impl cudaDeviceAttr

pub const cudaDevAttrL2CacheSize: cudaDeviceAttr

< Size of L2 cache in bytes

impl cudaDeviceAttr

pub const cudaDevAttrMaxThreadsPerMultiProcessor: cudaDeviceAttr

< Maximum resident threads per multiprocessor

impl cudaDeviceAttr

pub const cudaDevAttrAsyncEngineCount: cudaDeviceAttr

< Number of asynchronous engines

impl cudaDeviceAttr

pub const cudaDevAttrUnifiedAddressing: cudaDeviceAttr

< Device shares a unified address space with the host

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture1DLayeredWidth: cudaDeviceAttr

< Maximum 1D layered texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture1DLayeredLayers: cudaDeviceAttr

< Maximum layers in a 1D layered texture

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DGatherWidth: cudaDeviceAttr

< Maximum 2D texture width if cudaArrayTextureGather is set

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DGatherHeight: cudaDeviceAttr

< Maximum 2D texture height if cudaArrayTextureGather is set

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture3DWidthAlt: cudaDeviceAttr

< Alternate maximum 3D texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture3DHeightAlt: cudaDeviceAttr

< Alternate maximum 3D texture height

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture3DDepthAlt: cudaDeviceAttr

< Alternate maximum 3D texture depth

impl cudaDeviceAttr

pub const cudaDevAttrPciDomainId: cudaDeviceAttr

< PCI domain ID of the device

impl cudaDeviceAttr

pub const cudaDevAttrTexturePitchAlignment: cudaDeviceAttr

< Pitch alignment requirement for textures

impl cudaDeviceAttr

pub const cudaDevAttrMaxTextureCubemapWidth: cudaDeviceAttr

< Maximum cubemap texture width/height

impl cudaDeviceAttr

pub const cudaDevAttrMaxTextureCubemapLayeredWidth: cudaDeviceAttr

< Maximum cubemap layered texture width/height

impl cudaDeviceAttr

pub const cudaDevAttrMaxTextureCubemapLayeredLayers: cudaDeviceAttr

< Maximum layers in a cubemap layered texture

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface1DWidth: cudaDeviceAttr

< Maximum 1D surface width

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface2DWidth: cudaDeviceAttr

< Maximum 2D surface width

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface2DHeight: cudaDeviceAttr

< Maximum 2D surface height

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface3DWidth: cudaDeviceAttr

< Maximum 3D surface width

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface3DHeight: cudaDeviceAttr

< Maximum 3D surface height

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface3DDepth: cudaDeviceAttr

< Maximum 3D surface depth

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface1DLayeredWidth: cudaDeviceAttr

< Maximum 1D layered surface width

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface1DLayeredLayers: cudaDeviceAttr

< Maximum layers in a 1D layered surface

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface2DLayeredWidth: cudaDeviceAttr

< Maximum 2D layered surface width

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface2DLayeredHeight: cudaDeviceAttr

< Maximum 2D layered surface height

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurface2DLayeredLayers: cudaDeviceAttr

< Maximum layers in a 2D layered surface

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurfaceCubemapWidth: cudaDeviceAttr

< Maximum cubemap surface width

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurfaceCubemapLayeredWidth: cudaDeviceAttr

< Maximum cubemap layered surface width

impl cudaDeviceAttr

pub const cudaDevAttrMaxSurfaceCubemapLayeredLayers: cudaDeviceAttr

< Maximum layers in a cubemap layered surface

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture1DLinearWidth: cudaDeviceAttr

< Maximum 1D linear texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DLinearWidth: cudaDeviceAttr

< Maximum 2D linear texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DLinearHeight: cudaDeviceAttr

< Maximum 2D linear texture height

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DLinearPitch: cudaDeviceAttr

< Maximum 2D linear texture pitch in bytes

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DMipmappedWidth: cudaDeviceAttr

< Maximum mipmapped 2D texture width

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture2DMipmappedHeight: cudaDeviceAttr

< Maximum mipmapped 2D texture height

impl cudaDeviceAttr

pub const cudaDevAttrComputeCapabilityMajor: cudaDeviceAttr

< Major compute capability version number

impl cudaDeviceAttr

pub const cudaDevAttrComputeCapabilityMinor: cudaDeviceAttr

< Minor compute capability version number

impl cudaDeviceAttr

pub const cudaDevAttrMaxTexture1DMipmappedWidth: cudaDeviceAttr

< Maximum mipmapped 1D texture width

impl cudaDeviceAttr

pub const cudaDevAttrStreamPrioritiesSupported: cudaDeviceAttr

< Device supports stream priorities

impl cudaDeviceAttr

pub const cudaDevAttrGlobalL1CacheSupported: cudaDeviceAttr

< Device supports caching globals in L1

impl cudaDeviceAttr

pub const cudaDevAttrLocalL1CacheSupported: cudaDeviceAttr

< Device supports caching locals in L1

impl cudaDeviceAttr

pub const cudaDevAttrMaxSharedMemoryPerMultiprocessor: cudaDeviceAttr

< Maximum shared memory available per multiprocessor in bytes

impl cudaDeviceAttr

pub const cudaDevAttrMaxRegistersPerMultiprocessor: cudaDeviceAttr

< Maximum number of 32-bit registers available per multiprocessor

impl cudaDeviceAttr

pub const cudaDevAttrManagedMemory: cudaDeviceAttr

< Device can allocate managed memory on this system

impl cudaDeviceAttr

pub const cudaDevAttrIsMultiGpuBoard: cudaDeviceAttr

< Device is on a multi-GPU board

impl cudaDeviceAttr

pub const cudaDevAttrMultiGpuBoardGroupID: cudaDeviceAttr

< Unique identifier for a group of devices on the same multi-GPU board

impl cudaDeviceAttr

pub const cudaDevAttrHostNativeAtomicSupported: cudaDeviceAttr

< Link between the device and the host supports native atomic operations

impl cudaDeviceAttr

pub const cudaDevAttrSingleToDoublePrecisionPerfRatio: cudaDeviceAttr

< Ratio of single precision performance (in floating-point operations per second) to double precision performance

impl cudaDeviceAttr

pub const cudaDevAttrPageableMemoryAccess: cudaDeviceAttr

< Device supports coherently accessing pageable memory without calling cudaHostRegister on it

impl cudaDeviceAttr

pub const cudaDevAttrConcurrentManagedAccess: cudaDeviceAttr

< Device can coherently access managed memory concurrently with the CPU

impl cudaDeviceAttr

pub const cudaDevAttrComputePreemptionSupported: cudaDeviceAttr

< Device supports Compute Preemption

impl cudaDeviceAttr

pub const cudaDevAttrCanUseHostPointerForRegisteredMem: cudaDeviceAttr

< Device can access host registered memory at the same virtual address as the CPU

impl cudaDeviceAttr

pub const cudaDevAttrReserved92: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrReserved93: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrReserved94: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrCooperativeLaunch: cudaDeviceAttr

< Device supports launching cooperative kernels via ::cudaLaunchCooperativeKernel

impl cudaDeviceAttr

pub const cudaDevAttrCooperativeMultiDeviceLaunch: cudaDeviceAttr

< Deprecated, cudaLaunchCooperativeKernelMultiDevice is deprecated.

impl cudaDeviceAttr

pub const cudaDevAttrMaxSharedMemoryPerBlockOptin: cudaDeviceAttr

< The maximum optin shared memory per block. This value may vary by chip. See ::cudaFuncSetAttribute

impl cudaDeviceAttr

pub const cudaDevAttrCanFlushRemoteWrites: cudaDeviceAttr

< Device supports flushing of outstanding remote writes.

impl cudaDeviceAttr

pub const cudaDevAttrHostRegisterSupported: cudaDeviceAttr

< Device supports host memory registration via ::cudaHostRegister.

impl cudaDeviceAttr

pub const cudaDevAttrPageableMemoryAccessUsesHostPageTables: cudaDeviceAttr

< Device accesses pageable memory via the host’s page tables.

impl cudaDeviceAttr

pub const cudaDevAttrDirectManagedMemAccessFromHost: cudaDeviceAttr

< Host can directly access managed memory on the device without migration.

impl cudaDeviceAttr

pub const cudaDevAttrMaxBlocksPerMultiprocessor: cudaDeviceAttr

< Maximum number of blocks per multiprocessor

impl cudaDeviceAttr

pub const cudaDevAttrMaxPersistingL2CacheSize: cudaDeviceAttr

< Maximum L2 persisting lines capacity setting in bytes.

impl cudaDeviceAttr

pub const cudaDevAttrMaxAccessPolicyWindowSize: cudaDeviceAttr

< Maximum value of cudaAccessPolicyWindow::num_bytes.

impl cudaDeviceAttr

pub const cudaDevAttrReservedSharedMemoryPerBlock: cudaDeviceAttr

< Shared memory reserved by CUDA driver per block in bytes

impl cudaDeviceAttr

pub const cudaDevAttrSparseCudaArraySupported: cudaDeviceAttr

< Device supports sparse CUDA arrays and sparse CUDA mipmapped arrays

impl cudaDeviceAttr

pub const cudaDevAttrHostRegisterReadOnlySupported: cudaDeviceAttr

< Device supports using the ::cudaHostRegister flag cudaHostRegisterReadOnly to register memory that must be mapped as read-only to the GPU

impl cudaDeviceAttr

pub const cudaDevAttrTimelineSemaphoreInteropSupported: cudaDeviceAttr

< External timeline semaphore interop is supported on the device

impl cudaDeviceAttr

pub const cudaDevAttrMaxTimelineSemaphoreInteropSupported: cudaDeviceAttr

< Deprecated, External timeline semaphore interop is supported on the device

impl cudaDeviceAttr

pub const cudaDevAttrMemoryPoolsSupported: cudaDeviceAttr

< Device supports using the ::cudaMallocAsync and ::cudaMemPool family of APIs

impl cudaDeviceAttr

pub const cudaDevAttrGPUDirectRDMASupported: cudaDeviceAttr

< Device supports GPUDirect RDMA APIs, like nvidia_p2p_get_pages (see https://docs.nvidia.com/cuda/gpudirect-rdma for more information)

impl cudaDeviceAttr

pub const cudaDevAttrGPUDirectRDMAFlushWritesOptions: cudaDeviceAttr

< The returned attribute shall be interpreted as a bitmask, where the individual bits are listed in the ::cudaFlushGPUDirectRDMAWritesOptions enum

impl cudaDeviceAttr

pub const cudaDevAttrGPUDirectRDMAWritesOrdering: cudaDeviceAttr

< GPUDirect RDMA writes to the device do not need to be flushed for consumers within the scope indicated by the returned attribute. See ::cudaGPUDirectRDMAWritesOrdering for the numerical values returned here.

impl cudaDeviceAttr

pub const cudaDevAttrMemoryPoolSupportedHandleTypes: cudaDeviceAttr

< Handle types supported with mempool based IPC

impl cudaDeviceAttr

pub const cudaDevAttrClusterLaunch: cudaDeviceAttr

< Indicates device supports cluster launch

impl cudaDeviceAttr

pub const cudaDevAttrDeferredMappingCudaArraySupported: cudaDeviceAttr

< Device supports deferred mapping CUDA arrays and CUDA mipmapped arrays

impl cudaDeviceAttr

pub const cudaDevAttrReserved122: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrReserved123: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrReserved124: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrIpcEventSupport: cudaDeviceAttr

< Device supports IPC Events.

impl cudaDeviceAttr

pub const cudaDevAttrMemSyncDomainCount: cudaDeviceAttr

< Number of memory synchronization domains the device supports.

impl cudaDeviceAttr

pub const cudaDevAttrReserved127: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrReserved128: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrReserved129: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrNumaConfig: cudaDeviceAttr

< NUMA configuration of a device: value is of type ::cudaDeviceNumaConfig enum

impl cudaDeviceAttr

pub const cudaDevAttrNumaId: cudaDeviceAttr

< NUMA node ID of the GPU memory

impl cudaDeviceAttr

pub const cudaDevAttrReserved132: cudaDeviceAttr

impl cudaDeviceAttr

pub const cudaDevAttrMpsEnabled: cudaDeviceAttr

< Contexts created on this device will be shared via MPS

impl cudaDeviceAttr

pub const cudaDevAttrHostNumaId: cudaDeviceAttr

< NUMA ID of the host node closest to the device. Returns -1 when system does not support NUMA.

impl cudaDeviceAttr

pub const cudaDevAttrD3D12CigSupported: cudaDeviceAttr

< Device supports CIG with D3D12.

impl cudaDeviceAttr

pub const cudaDevAttrMax: cudaDeviceAttr

Trait Implementations

impl Clone for cudaDeviceAttr

fn clone(&self) -> cudaDeviceAttr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for cudaDeviceAttr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for cudaDeviceAttr

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for cudaDeviceAttr

fn eq(&self, other: &cudaDeviceAttr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for cudaDeviceAttr

impl Eq for cudaDeviceAttr

impl StructuralPartialEq for cudaDeviceAttr